Fin field-effect transistors (FinFET) are multi-gate transistors where the conducting channel is wrapped around a thin piece of silicon, often referred to and configured as a “fin.” The dimensions of the fin structure determine the effective channel width of the transistor. Typically, the source, drain and gate are formed extending above the substrate, and the FinFET is viewed as a MOSFET device with a folded gate feature. FinFETs provide a promising candidate for small line width technology because of their excellent short channel effect control, scalability and higher current drive per unit width.
Turning to FIGS. 1A and 1B, there is illustrated a conventional prior art FinFET device 100 in FIG. 1A. FIG. 1B illustrates the relevant cross-section of the prior art FinFET device 100 along line 1B-1B. The device 100 includes a first source/drain (S/D) region 102, a second S/D region 104, a fin structure 106 and a gate electrode 108, all disposed on a substrate 120. The fin structure 106 includes a first fin portion 106a, a second fin portion 106b, a channel portion 106c and vertical sidewalls 107. Disposed between the channel portion 106c and the gate electrode 108 is a gate (insulator) 110 (shown in FIG. 1B).
As will be appreciated, a portion of the gate electrode 108 that normally overlies the channel portion 106c has been omitted in FIG. 1A (but is shown in FIG. 1B) to facilitate an understanding of the present disclosure. It will be understood that the first fin portion 106a forms part of the S/D region 102 while the second fin portion 106b forms part of the S/D region 104. In addition, as shown in FIG. 1B, a relatively thick dielectric layer 112 is disposed on top of the channel portion 106c between the channel portion 106c and the gate electrode 108.
It will also be understood that, depending on the type of FET desired, the S/D regions 102, 104 (and the exposed portions of the fin structure 106a, 106b not under the gate) will be doped with either n-type or p-type impurities, while the channel portion 106c beneath the gate electrode 108 will be doped with the opposite type—either p-type or n-type, respectively (usually doped as part of the initial starting substrate material).
Conventional MOS fabrication typically utilizes a silicon substrate having (100) surface orientation (such as in the FinFET device 100). Utilization of the (100) surface orientation is preferred due to the large application of nFETs and the higher electron mobility in the nFETs resulting from the (100) surface orientation. However, the (100) surface orientation limits hole mobility and thus degrades pFET performance.
Accordingly, there is a need for new p-channel FinFET device and structure (and methods of manufacture/fabrication) that increases hole mobility and enhances pFET performance.